NHD-0440AZ-FL-GBW【PDF 9/10 页】LCD MOD CHAR 4X40 Y/G TRANSFL

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NHD-0440AZ

F: Display line number control bit

When F=“Low”, 5x8 dots format display mode is set.

When F=“High”, 5x11 dots format display mode.

7) Set CGRAM address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 AC5 AC4 AC3 AC2 AC1 AC0

Set CGRAM address to AC.

The instruction makes CGRAM data available from MPU.

8) Set DDRAM address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 AC6 AC5 AC4 AC3 AC2 AC1 AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available form MPU.

When 1-line display mode (N=LOW), DDRAM address is form “00H” to “4FH”. st

line form “00H” to “27H”, and DDRAM address

line is from “40H” to “67H”.

In 2-line display mode (N=High), DDRAM address in the 1

In the 2

9) Read busy flag & address

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

This instruction shows whether KS0066U is in internal operation or not.

If the resultant BF is “High”, internal operation is in

progress and should wait BF is to be LOW, which by then if the nest

instruction can be performed. In this instruction you can also read the value of the address counter.

10) Write data to RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 D7 D6 D5 D4 D3 D2 D1 D0

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM address set,

CGRAM address set).

RAM set instruction can also determine the AC direction to RAM.

After write operation. The address is automatically increased/decreased by 1, according to the entry mode.

11) Read data from RAM

RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 D7 D6 D5 D4 D3 D2 D1 D0

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM is not

performed before this instruction, the data that has been read first is invalid, as the direction of AC is not yet determined.

If RAM data is read several times without RAM address instructions set before, read operation, the correct RAM data

can be obtained from the second. But the first data would be incorrect, as there is no time margin to transfer RAM data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set instruction,

It also transfers RAM data to

output data register.

After read operation, address counter is automatically increased/decreased by 1 according to the entry mode.

V: A 7/9 01/31/2007

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